• X-Stack PI Meeting
    05/28/2014 - 05/29/2014
    Cambridge
    Massachusetts

X-Stack PI Meeting

Runtime Systems

Moderator: Vivek Sarkar

Panelists: Ron Brightwell, David Grove, Sanjay Kale, Wilf Pinfold, Kathy Yelick

We have presented the results of the Runtime Summit, which include challenges, solutions, a set of important questions to be answered, and a vision for a runtime architecture, with major components, interfaces, and how to measure success.

This session will focus on getting feedback from selected panelists and the audience on our results. Panelists will first provide us with constructive criticism and suggestions, followed by the interaction with the audience.

Questions and Discussion

Runtime Systems Vision Panel Summary

Compilers and Auto-tuning

Moderator: Mary Hall

Panelists: Saman Amarasinghe, Una-May O'Reilly, Dan Quinlan

Panel description.

Questions and Discussion

Compiler Panel Summary

OpenTuner

Languages and DSLs

Moderator: Dan/Saman

Panelists: Mary Hall, David Padua, Anshu Dubey, Katherine Yelick, Saday Sadayappan, Shoaib Kamil

Panel description.

Questions and Discussion

GPLs and and DSLs Panel Summary)

Mapping and Optimization Framework

Moderator: Armando Solar-Lezama

Panelist: Mary Hall (University of Utah), David Padua (UIUC), Muthu Baskaran (Reservoir Labs), Shoaib Kamil (MIT)

Panel description: The panel will consist of short (8 min) presentations by each panelist on their views on new approaches to map high-level representations of a computation down to an efficient implementation specialized for a particular platform.

Questions and Discussion

Mapping Framework Panel Summary)

Resilience

Moderators: Andrew A. Chien and Mattan Erez

Panelists: Kath Knobe, Dan Quinlan, Vivek Sarkar, Martin Schulz, Sriram Krishnamoorthy, Michael Carbin, and the moderators.

A focused discussion on how resilience should reflected in the X-stack runtime abstract architecture and the critical research technologies.

Questions and Discussion

Resilience Panel Summary

Resilience and CnC - Kath Knobe

Simulation technology

Moderator: Wilfred Pinfold

Panelists: John Shalf, Jeff Vetter, Arun Rodrigues, Romain Cledat

Panel description: Simulators are tools for getting a job done. There are many jobs we can use simulators for in designing an Exascale system. First there are simulators for use in various stages of design; conceptual, functionality, final (cycle accurate). Then there are simulators for CPU, memory, network, storage, IO. Finally there are simulators to explore different machine characteristics such as power, resilience or performance. These simulators can be designed to work separately, as cooperating parts or as an integrated system simulation. In this panel we will explore the simulators in use today, the benefits and challenges of integration and the direction we should take to optimize system design and minimize effort expended on tool development.

Questions and Discussion

Simulation Technology Panel Summary

X-Stack OS/R requirements

Moderator: Ron Brightwell(SNL), Steve Hofmeyr (LBNL), Marc Snir (ANL) and Barney Maccabe (ORNL)

Panelists: Vivek Sarkar (Rice), Shekhar Borkar (Intel), John Feo (PNL), Pat McCormick (LANL), Martin Schulz (LLNL), Brian Van Straalen (LBL)

Panel description: The intent of this panel is to collect requirements from people developing architectures, tools, and runtime systems.

Questions and Discussion

OS/R Requirments Panel Summary)

Performance Tools and Their Interfaces for the X-Stack

Moderator: Martin Schulz (LLNL)

This panel will discuss the role of performance tools in the exascale software stacks: which tools will users expect and which questions should they address, what abstractions should they map their results to and what interfaces in the X-Stack will be available for tools to require the necessary information?

Panelists: Ron Brightwell (SNLs), Romain Cledat (Intel), Jeff Hollingsworth (UMD), John Mellor-Crummey (Rice), Brian Van Straalen (LBL)

Questions and Discussion

X-Stack Interfaces Panel Summary

 

Technology Marketplace Description

The Technology Marketplace will be a place for peer-to-peer, at-the-laptop live demos and discussion of technologies being developed in the X-Stack portfolio and in coordinating programs.

A conference room will be set up with 15-20 tables, with two technologies per table. The demo giver will bring your laptop and work from that, or plan to log into your home systems (Wi-Fi and power provided). Browse an EMACS buffer to show compiler input and output, try new permutations suggested by your peers, show makefiles, time the wall clock, interact with visualizations. Show the places where the technology smokes the competition, and the unvarnished truth where your technology gives off smoke from stress. Plan for 4-5 people sitting with you looking over your shoulder, sharing ideas, asking questions, and innovating with you.

For accompanying materials, you can bring a small poster, or better yet, a printout of the concepts, schematics, and equations. Flipchart easels will be provided for you to sketch concepts live. We expect high participation of X-Stack performers, several technologies per team.

Technologies will be grouped by special interest sessions. The sessions are listed below with their organizers.

Organizers of the technology marketplace sessions should be contacting you to discuss your participation in their session. If you are not contacted by COB May 14, and would like to participate, please write to me, sonia.sachs@science.doe.gov.

 

Runtime Systems Technology Marketplace

Session Organizer: Vivek Sarkar, vsarkar@Rice.edu

Participants:

Laxmikant (Sanjay) Kale: Charm++ RTS demos on resilience, and temperature-power-aware optimizations.

Compilers and Auto-tuning Technology Marketplace

Session Organizer: Mary Hall, mhall@cs.utah.edu

Participants:

 

Languages and DSLs Technology Marketplace

Session Organizers: Dan Quinlan, quinlan1@llnl.gov and Saman Amarasinghe, saman@csail.mit.edu

Participants:

 

Mapping and Optimization Framework Technology Marketplace

Session Organizer: Armando Solar-Lezama, asolar@csail.mit.edu

Participants:

  • DSL example: X-GEN for Directive-Based Heterogeneous Computing, by Chunhua "Leo" Liao

Resilience Technology Marketplace

Session Organizers: Andrew A. Chien, achien@cs.uchicago.edu and Mattan Erez, mattan.erez@mail.utexas.edu

Participants:

  • Data-oriented, User-controlled Resilience with Global View Resilience (Hajime Fujita, Nan Dun), includes OpenMC, Chombo, and ddcMD demonstrations
  • DEGAS resilience technologies (Mattan Erez):
    • Using Berkeley Lab's Checkpoint/Restart: Application Programming Interfaces and Operating System Interfaces (LBNL)
    • Containment Domains for Scalable and Efficient Resilience (UT Austin)
    • Affinity-Aware Checkpoint/Restart (NCST)

Simulation Technology Marketplace

Session Organizers: Shekhar Borkar, shekhar.y.borkar@intel.com and Wilfred Pinfold,wilfred.pinfold@intel.com

Participants: Arun Rodrigues, Romain Cledat, Jeff Vetter

  • OCR on FSIM
  • SST's new GUI
  • ExaSAT compiler/performance analysis tool
  • Blackcomb

Performance Tools Technology Marketplace

Session Organizers: Martin Schulz, schulzm@llnl.gov

Participants:

MemAxes - A new tool for memory performance visualization

Martin Schulz, LLNL

 * Examples on XSBench and Lulesh

HPCToolkit and DOE codes

John Mellor-Crummey, Rice Unversity

 * NWChem (global arrays)
 * madness (massive threading + templates)
 * lulesh (massive inlining)
 * open community runtime

Emerging Memory Technology Marketplace

Session Organizers: Jeffrey Vetter, vetter@ornl.gov, and Xipeng Shen, xshen@cs.wm.edu

Participants:

Venue

MIT - Stratton Student Center
84 Massachusetts Ave
Cambridge, MA 02139
United States

Involved Programs/Projects

Sonia Sachs

Agenda

Agenda May 28

Time

Topic Presenter
  Opening Remarks Sonia Sachs
8:00 am - 8:25 am D-­TEC: DSL Technology for Exascale Computing Dan Quinlan,LLNL, Saman Amarasinghe,MIT
8:25 am - 8:50 am XPRESS: eXascale Programming Environment and System Software Ron Brightwell,Sandia
8:50 am - 9:15 am Traleika Glacier Shekhar Borkar,Intel
9:15 am - 9:40 am DEGAS: Dynamic Exascale Global Address Space Kathy Yelick,LBNL
9:40 am - 10:05 am PIPER: Performance Insight For Programmers and Exascale Runtimes Martin Schulz, LLNL
10:05 am - 10:20 am break
10:20 am - 10:45 am X-TUNE: Autotuning for Exascale Mary Hall,U. Utah
10:45 am - 11:10 am SLEEC: Semantics-rich Libraries for Effective Exascale Computation Milind Kulkarni,Purdue
11:10 am - 11:35 am GVR: Exploiting Global View for Resilience Andrew Chien,U.Chicago
11:35 am - 12:00 pm Dynax: Dynamic Adaptive X-Stack Prof. Gao, ETI
12:00 pm - 12:25 pm CORVETTE: Program Correctness Verification and Testing for Exascale Koushik Sen, U.C.Berkeley
12:25 pm - 1:15 pm lunch
1:15 pm - 1:45 pm SST, CodeX, Blackcomb Arun Rodrigues,Sandia, John Shalf,LBNL, Jeff Vetter,ORNL
1:45 pm - 2:30 pm ARGO, HOBBES, and X-ARCC Marc Snir,ANL, Barney Maccabe,ORNL, Ron Brightwell,Sandia, Steve Hofmeyr,LBNL
2:30 pm - 3:00 pm DSLs for DoE Applications Saman Amarasinghe, MIT
3:00 pm - 3:15 pm break
3:15 pm - 3:40 pm Apps on HPX Alice Koniges, LBNL
3:40 pm - 4:05 pm Apps on OCR Roger Golliver, UIUC
4:05 pm - 4:30 pm Apps on Charm++ Sanjay Kale, UIUC
4:30 pm - 5:00 pm Modelado Foundation

Wilfred Pinfold, Intel

Agenda May 29

Time Topic Presenter
8:00 – 8:25 The postdoc pool work Jim Belak, LLNL
8:25 – 8:50 Abstract machine model and proxy architectures John Shalf, LBNL
8:50 – 9:15 Runtime Systems Summit summary Vivek Sarkar, Rice
9:15 - 9:30 Runtime Systems and Programming Environments for the Future Lauren Smith, DOD
9:30 – 10:30 Panel Session 1
10:30 – 10:45 Break
10:45 – 11:45 Panel Session 2
11:45 – 2:00 Working lunch – Technology Marketplace - floor 3 coffee house
2:00 – 3:00 Panel Session 3
3:00 – 3:15 Break
3:15 – 4:40 Panel Summaries (10 minutes each)
4:40 – 5:00 Closing remarks and Q&A Sonia Sachs

 

Runtime Systems

Moderator: Vivek Sarkar

Panelists: Ron Brightwell, David Grove, Sanjay Kale, Wilf Pinfold, Kathy Yelick

We have presented the results of the Runtime Summit, which include challenges, solutions, a set of important questions to be answered, and a vision for a runtime architecture, with major components, interfaces, and how to measure success.

This session will focus on getting feedback from selected panelists and the audience on our results. Panelists will first provide us with constructive criticism and suggestions, followed by the interaction with the audience.

Questions and Discussion

Runtime Systems Vision Panel Summary

Compilers and Auto-tuning

Moderator: Mary Hall

Panelists: Saman Amarasinghe, Una-May O'Reilly, Dan Quinlan

Panel description.

Questions and Discussion

Compiler Panel Summary

OpenTuner

Languages and DSLs

Moderator: Dan/Saman

Panelists: Mary Hall, David Padua, Anshu Dubey, Katherine Yelick, Saday Sadayappan, Shoaib Kamil

Panel description.

Questions and Discussion

GPLs and and DSLs Panel Summary)

Mapping and Optimization Framework

Moderator: Armando Solar-Lezama

Panelist: Mary Hall (University of Utah), David Padua (UIUC), Muthu Baskaran (Reservoir Labs), Shoaib Kamil (MIT)

Panel description: The panel will consist of short (8 min) presentations by each panelist on their views on new approaches to map high-level representations of a computation down to an efficient implementation specialized for a particular platform.

Questions and Discussion

Mapping Framework Panel Summary)

Resilience

Moderators: Andrew A. Chien and Mattan Erez

Panelists: Kath Knobe, Dan Quinlan, Vivek Sarkar, Martin Schulz, Sriram Krishnamoorthy, Michael Carbin, and the moderators.

A focused discussion on how resilience should reflected in the X-stack runtime abstract architecture and the critical research technologies.

Questions and Discussion

Resilience Panel Summary

Resilience and CnC - Kath Knobe

Simulation technology

Moderator: Wilfred Pinfold

Panelists: John Shalf, Jeff Vetter, Arun Rodrigues, Romain Cledat

Panel description: Simulators are tools for getting a job done. There are many jobs we can use simulators for in designing an Exascale system. First there are simulators for use in various stages of design; conceptual, functionality, final (cycle accurate). Then there are simulators for CPU, memory, network, storage, IO. Finally there are simulators to explore different machine characteristics such as power, resilience or performance. These simulators can be designed to work separately, as cooperating parts or as an integrated system simulation. In this panel we will explore the simulators in use today, the benefits and challenges of integration and the direction we should take to optimize system design and minimize effort expended on tool development.

Questions and Discussion

Simulation Technology Panel Summary

X-Stack OS/R requirements

Moderator: Ron Brightwell(SNL), Steve Hofmeyr (LBNL), Marc Snir (ANL) and Barney Maccabe (ORNL)

Panelists: Vivek Sarkar (Rice), Shekhar Borkar (Intel), John Feo (PNL), Pat McCormick (LANL), Martin Schulz (LLNL), Brian Van Straalen (LBL)

Panel description: The intent of this panel is to collect requirements from people developing architectures, tools, and runtime systems.

Questions and Discussion

OS/R Requirments Panel Summary)

Performance Tools and Their Interfaces for the X-Stack

Moderator: Martin Schulz (LLNL)

This panel will discuss the role of performance tools in the exascale software stacks: which tools will users expect and which questions should they address, what abstractions should they map their results to and what interfaces in the X-Stack will be available for tools to require the necessary information?

Panelists: Ron Brightwell (SNLs), Romain Cledat (Intel), Jeff Hollingsworth (UMD), John Mellor-Crummey (Rice), Brian Van Straalen (LBL)

Questions and Discussion

X-Stack Interfaces Panel Summary

Resources

Presentations

Abstract machine model and proxy architectures, John Shalf, LBNL
Apps on Charm++, Sanjay Kale, UIUC
Apps on HPX, Alice Koniges, LBNL
Apps on OCR, Roger Golliver, UIUC
ARGO, HOBBES, and X-ARCC, Marc Snir, ANL
Blackcomb: Hardware-Software Co-design for NonVolatile Memory in Exascale Systems, Jeff Vetter
CoDEx: CoDesign for Exascale, John Shalf, LBNL
CORVETTE: Program Correctness, Verification, and Testing for Exascale, Koushik Sen, UC Berkeley
SST, Arun Rodrigues, Sandia
The postdoc pool work, Jim Belak, LLNL
Why DSLs Are Desirable, Anshu
Why DSLs are Important to the DoE Exascale Mission, Saman Amarasinghe, MIT
XPRESS Project Update, Ron Brightwell, Sandia