Moderator: Vivek Sarkar
Panelists: Ron Brightwell, David Grove, Sanjay Kale, Wilf Pinfold, Kathy Yelick
We have presented the results of the Runtime Summit, which include challenges, solutions, a set of important questions to be answered, and a vision for a runtime architecture, with major components, interfaces, and how to measure success.
This session will focus on getting feedback from selected panelists and the audience on our results. Panelists will first provide us with constructive criticism and suggestions, followed by the interaction with the audience.
Compilers and Auto-tuning
Moderator: Mary Hall
Panelists: Saman Amarasinghe, Una-May O'Reilly, Dan Quinlan
Languages and DSLs
Panelists: Mary Hall, David Padua, Anshu Dubey, Katherine Yelick, Saday Sadayappan, Shoaib Kamil
Mapping and Optimization Framework
Moderator: Armando Solar-Lezama
Panelist: Mary Hall (University of Utah), David Padua (UIUC), Muthu Baskaran (Reservoir Labs), Shoaib Kamil (MIT)
Panel description: The panel will consist of short (8 min) presentations by each panelist on their views on new approaches to map high-level representations of a computation down to an efficient implementation specialized for a particular platform.
Moderators: Andrew A. Chien and Mattan Erez
Panelists: Kath Knobe, Dan Quinlan, Vivek Sarkar, Martin Schulz, Sriram Krishnamoorthy, Michael Carbin, and the moderators.
A focused discussion on how resilience should reflected in the X-stack runtime abstract architecture and the critical research technologies.
Resilience and CnC - Kath Knobe
Moderator: Wilfred Pinfold
Panelists: John Shalf, Jeff Vetter, Arun Rodrigues, Romain Cledat
Panel description: Simulators are tools for getting a job done. There are many jobs we can use simulators for in designing an Exascale system. First there are simulators for use in various stages of design; conceptual, functionality, final (cycle accurate). Then there are simulators for CPU, memory, network, storage, IO. Finally there are simulators to explore different machine characteristics such as power, resilience or performance. These simulators can be designed to work separately, as cooperating parts or as an integrated system simulation. In this panel we will explore the simulators in use today, the benefits and challenges of integration and the direction we should take to optimize system design and minimize effort expended on tool development.
X-Stack OS/R requirements
Moderator: Ron Brightwell(SNL), Steve Hofmeyr (LBNL), Marc Snir (ANL) and Barney Maccabe (ORNL)
Panelists: Vivek Sarkar (Rice), Shekhar Borkar (Intel), John Feo (PNL), Pat McCormick (LANL), Martin Schulz (LLNL), Brian Van Straalen (LBL)
Panel description: The intent of this panel is to collect requirements from people developing architectures, tools, and runtime systems.
Performance Tools and Their Interfaces for the X-Stack
Moderator: Martin Schulz (LLNL)
This panel will discuss the role of performance tools in the exascale software stacks: which tools will users expect and which questions should they address, what abstractions should they map their results to and what interfaces in the X-Stack will be available for tools to require the necessary information?
Panelists: Ron Brightwell (SNLs), Romain Cledat (Intel), Jeff Hollingsworth (UMD), John Mellor-Crummey (Rice), Brian Van Straalen (LBL)
Technology Marketplace Description
The Technology Marketplace will be a place for peer-to-peer, at-the-laptop live demos and discussion of technologies being developed in the X-Stack portfolio and in coordinating programs.
A conference room will be set up with 15-20 tables, with two technologies per table. The demo giver will bring your laptop and work from that, or plan to log into your home systems (Wi-Fi and power provided). Browse an EMACS buffer to show compiler input and output, try new permutations suggested by your peers, show makefiles, time the wall clock, interact with visualizations. Show the places where the technology smokes the competition, and the unvarnished truth where your technology gives off smoke from stress. Plan for 4-5 people sitting with you looking over your shoulder, sharing ideas, asking questions, and innovating with you.
For accompanying materials, you can bring a small poster, or better yet, a printout of the concepts, schematics, and equations. Flipchart easels will be provided for you to sketch concepts live. We expect high participation of X-Stack performers, several technologies per team.
Technologies will be grouped by special interest sessions. The sessions are listed below with their organizers.
Organizers of the technology marketplace sessions should be contacting you to discuss your participation in their session. If you are not contacted by COB May 14, and would like to participate, please write to me, email@example.com.
Runtime Systems Technology Marketplace
Session Organizer: Vivek Sarkar, vsarkar@Rice.edu
Laxmikant (Sanjay) Kale: Charm++ RTS demos on resilience, and temperature-power-aware optimizations.
Compilers and Auto-tuning Technology Marketplace
Session Organizer: Mary Hall, firstname.lastname@example.org
Languages and DSLs Technology Marketplace
Mapping and Optimization Framework Technology Marketplace
Session Organizer: Armando Solar-Lezama, email@example.com
- DSL example: X-GEN for Directive-Based Heterogeneous Computing, by Chunhua "Leo" Liao
Resilience Technology Marketplace
- Data-oriented, User-controlled Resilience with Global View Resilience (Hajime Fujita, Nan Dun), includes OpenMC, Chombo, and ddcMD demonstrations
- DEGAS resilience technologies (Mattan Erez):
- Using Berkeley Lab's Checkpoint/Restart: Application Programming Interfaces and Operating System Interfaces (LBNL)
- Containment Domains for Scalable and Efficient Resilience (UT Austin)
- Affinity-Aware Checkpoint/Restart (NCST)
Simulation Technology Marketplace
Participants: Arun Rodrigues, Romain Cledat, Jeff Vetter
- OCR on FSIM
- SST's new GUI
- ExaSAT compiler/performance analysis tool
Performance Tools Technology Marketplace
Session Organizers: Martin Schulz, firstname.lastname@example.org
MemAxes - A new tool for memory performance visualization
Martin Schulz, LLNL
* Examples on XSBench and Lulesh
HPCToolkit and DOE codes
John Mellor-Crummey, Rice Unversity
* NWChem (global arrays) * madness (massive threading + templates) * lulesh (massive inlining) * open community runtime
Emerging Memory Technology Marketplace